The present invention relates to an observation apparatus, observation method and program. In particular, the present invention relates to an observation apparatus, observation method and program, which observe an operation of an observation target apparatus.
Techniques which support the debugging of a designed logic circuit are disclosed in the following documents: “Hardware Design Verification Technique Based on Signal State Change and State Transition” by Koji Takano and Nobuyuki Ohba, Program and Proceedings of 18th Karuizawa Workshop on Circuit and System, pp. 563-568, Apr. 25, 2005 (hereinafter referred to as Non-patent Document 1); Japanese Patent Laid-Open Official Gazette No. 2002-10064 (hereinafter referred to as Patent Document 1); Japanese Patent Laid-Open Official Gazette No. Hei-9(1997)-130354 (hereinafter referred to as Patent Document 2); Japanese Patent Laid-Open No. Hei-7(1995)-111042 (hereinafter referred to as Patent Document 3); Published Translation of PCT Application No. 2003-526859 (hereinafter referred to as Patent Document 4); U.S. Pat. No. 5,576,979 (hereinafter referred to as Patent Document 5); U.S. Pat. No. 6,289,489 (hereinafter referred to as Patent Document 6); U.S. Pat. No. 5,920,711 (hereinafter referred to as Patent Document 7); U.S. Pat. No. 6,553,514 (hereinafter referred to as Patent Document 8); U.S. Pat. No. 6,751,582 (hereinafter referred to as Patent Document 9); and U.S. Pat. No. 6,647,513 (hereinafter referred to as Patent Document 10). Non-patent Document 1 describes that signals are observed on a per-transaction basis.
Patent Document 1 describes that digital data streams are classified in accordance with the features. Patent Document 2 describes that digital data is classified on a per-packet basis. Patent Document 3 describes that reduction in amplitude of a signal wave caused by inter-code interference is corrected. Patent Document 4 describes that signals are periodically decomposed to perform a statistical hypothesis test.
Patent Document 5 describes that creation of a timing diagram of an electronic circuit is supported. Patent Document 6 describes that a hardware description language (HDL) for logic circuit is associated with a state of the logic circuit displayed via a graphical user interface (GUI) to enable cross reference. Patent Document 7 describes that a hardware description for logic circuit, where a communication protocol designated by a user is implemented, is generated. Patent Document 8 describes that formal verification is carried out based on a result of software simulation. Patent Document 9 describes that GUI for carrying out efficient formal verification is provided. Patent Document 10 describes that a test case for function verification is efficiently provided to display coverage of verification items.
Verification techniques for a designed logic circuit include a method in which a logic circuit to be verified is converted to hardware such as a device, e.g., FPG or a prototype of an actual device so as to carry out verification. Verification using conversion to hardware makes it possible to verify failure occurred in a state where parts are connected.
Incidentally, in the case of verification using hardware, since the number of parts is large, massive signal transitions occur. Furthermore, since the logic circuit to be verified operates in a real time, the logic circuit has to be verified at high speed. In contrast to this, when debugging proceeds, frequency of occurrence of failure decreases to, for example, about once per several days. This makes it difficult to specify which timing failure occurs at.
Non-patent Documents 1 and 2 propose that signals outputted from the observation target apparatus are observed on a per-transaction basis for the purpose of solving the aforementioned problem. When the signals outputted from the observation target apparatus are observed on a per-transaction basis, it is possible to discover a transaction with a low frequency of occurrence without having foreknowledge. Accordingly, even in the case of verifying a system having a large number of parts and operating at high speed, it is possible to efficiently analyze behavior that a user does not expect, failure with a low frequency of occurrence and the like.
However, for separating signals into transactions, the user, for example, presets a division condition to thereby cause improvement in analytic efficiency to be hampered.